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advancement of FPGA technology has made possible a new way of
executing programs known as Reconfigurable Computing (RC). At
the lowest level all software instructions are executed on hardware.
It would be faster to skip the processor altogether and have
a custom hardware solution. For the most part this is not done
because of the development cost, but reconfigurable FPGAs allow
almost any hardware to be quickly built during run-time. My
research deals with the ability to instantiate programs in a
language such as Java on an FPGA instead of custom hardware
in order to dramatically speed up the execution time of these
programs.
Within a program, major pieces of code can be translated
into a hardware instantiation that is rectangular in shape.
One of the major considerations in such a scheme is the placement
of these rectangular modules onto the chip in the most efficient
manner. The factors that must be considered include: the routing
resources necessary to connect modules, fragmentation, and
the amount of time needed to reconfigure the chip.
This summer, I am working on a placement package to simulate
placing modules on the FPGA in order to determine the most
efficient placement for a variety of configurations. Determining
which configurations to place is a fairly nontrivial problem.
The decisions depend on the modules and their connectivity
as well as what point in the program is currently running.
In addition, the modules all have to fit on the chip. When
the placements are made, the final task is to create a model
that chooses the correct configurations and efficiently switches
between them as the program progresses.
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